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PI74VCX16373
16-Bit Transparent D-Type Latch with 3-State Outputs
Features
* The PI74VCX Family is designed for low voltage operation, VDD = 1.8V to 3.6V * 3.6V I/O Tolerant Inputs and Outputs * Supports Live Insertion * Balanced Drive, 24mA * Uses patented Noise Reduction Circuitry * Typical VOLP (Output Ground Bounce) < 0.6V at VDD = 2.5V, TA = 25C * Typical VOHV (Output VOH Undershoot) < -0.6V at VDD = 2.5V, TA = 25C * Power-Off high impedance inputs and outputs * Industrial operation at -40C to +85C * Packaging (Pb-free & Green available): - 48-pin 240-mil wide plastic TSSOP (A)
Description
Pericom Semiconductor's PI74VCX16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8bit latches or one 16-bit latch. When the Latch Enable (LE) input is HIGH, the Q outputs follow the (D) inputs. When LE is taken LOW, the Q outputs are latched at the levels set up at the D inputs. A buffered Output Enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state in which the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VDD through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The PI74VCX family is I/O Tolerant, allowing it to operate in mixed 1.8V/3.6V systems.
Block Diagram
1OE
1
1LE
48
C1
2
1Q1
1D1
47
1D
To Seven Other Channels
24
2OE 2LE
25
C1
13
2Q1
2D1
36
1D
To Seven Other Channels
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PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
Pin Description
Pin Name OE LE Dx Qx GND VDD Description Output Enable Input (Active LOW) Latch Enable (Active HIGH) Data Inputs 3-State Outputs Ground Power
Truth Table(1)
Inputs OE L L L H
Notes: 1. H L X Z = = = =
Outputs D H L X X Q H L Q0 Z
LE H H L X
High Signal Level Low Signal Level Don't Care or Irrelevant High Impedance
Pin Configuration
1OE 1Q1 1Q2 GND 1Q3 1Q4 VDD 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VDD 2Q5 2Q6 GND 2Q7 2Q8 2OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1LE 1D1 1D2 GND 1D3 1D4 VDD 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VDD 2D5 2D6 GND 2D7 2D8 2LE
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PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage Range, VDD .............................................. -0.5V to 4.6V Input Voltage Range, VI ....................................................... -0.5V to 4.6V Output Voltage Range, VO (3-Stated) .......................... -0.5V to 4.6V Output Voltage Range, VO(1) (Active) ............ -0.5V to VDD + 0.5V DC Input Diode Current (IIK) VI < 0V .................................... -50mA DC Output Diode Current (IOK) VO < 0V ................................................................................ -50mA VO > VDD ......................................................................................... -50mA DC Output Source/Sink Current (IOH/IOL) ............................ 50mA DC VDD or GND Current per Supply Pin (ICC or GND) .... 100mA Storage Temperature Range, TSTG ............................ -65C to150C
Notes: 1. Absolute maximum of IO must be observed. Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions(1)
Parame te rs VDD VIH VIL VI VO De s cription Supply voltage Data Retention Only High- level input voltage Low- level input voltage Input voltage Active State Output voltage Off State Output current in IOH/IOL t/v TA Input transistion rise or fall rate(2) Operating free- air temperature VDD = 3.0V to 3.6V VDD = 2.3V to 2.7V VDD = 1.8V 0 - 40 0 VDD = 2.7V to 3.6V VDD = 2.7V to 3.6V - 0 .3 0 1.2 2.0 0 .8 3 .6 VDD 3.6 24 18 6 10 85 mA ns/V C V 3.6 Conditions Operating M in. 1.8 M a x. 3.6 Units
Notes: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 2. As measured between 0.8V and 2.0V, VDD = 3.0V.
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PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V < VDD 3.6V)
Parame te rs VIH VIL De s cription HIGH Level Input Voltage LOW Level Input Voltage IOH = -100 A VOH HIGH Level Output Voltage IOH = -12 mA IOH = -18 mA IOH = -24 mA IOL = 100 A VOL LOW Level Output Voltage IOL = 12 mA IOL = 18 mA IOL = 24 mA II IOZ IOFF IDD IDD Input Leakage Current 3- STATE Output Leakage Power- OFF Leakage Current Quiescent Supply Current VI = 0.0V, V1 = 3.6V 0 VO 3.6V VI = VIH or VIL 0 (VI,VO) 3.6V VI = VDD to GND VDD (VI,VO) 3.6V VIH = VDD - 0.6V, Other inputs at VDD or GND 2.7 - 3.6 3.6 2.7 - 3.6 0 2.7 3.0 2.2 2 . 7 - 3 .6 2. 7 3.0 0.5 5 .0 10 10 20 20 750 0.2 0 .4 0.4 2.7 - 3.6 VDD - 0.2 2.2 2.4 V Conditions VDD M in. 2.0 0.8 Typ. M a x. Units
A
Increase in IDD per input
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PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
DC Characteristics (2.3V VDD 2.7V)
Parame te rs VIH VIL De s cription HIGH Level Input Voltage LOW Level Input Voltage IOH = - 100A VOH HIGH Level Output Voltage IOH = - 6mA IOH = - 12mA IOH = - 18mA IOL = 100A VOL LOW Level Output Voltage IOL = 12mA 2.3 IOL = 18mA II IOZ IOFF IDD Input Leakage Current 3- STATE Output Leakage V1 = 0.0V, V1 = 2.7V 0 VO 3.6V VI = VIH or VIL 2. 7 2.3 - 2.7 0 2.3 - 2.7 20 0. 4 5.0 10 10 20 A 2.3 - 2.7 2.3 2.3 - 2.7 VDD - 0.2 2.0 1.8 1.7 0. 2 0.4 V Conditions VDD M in. 1. 6 0.7 Typ. M ax. Units
Power- OFF Leakage Current 0 (VI,VO) 3.6V VI = VDD or GND Quiescent Supply Current VDD (VI,VO) 3.6V
DC Characteristics (1.8V VDD 2.3V)
Parame te rs VIH VIL VOH De s cription HIGH Level Input Voltage 1. 8 - 2 . 3 LOW Level Input Voltage HIGH Level Output Voltage IOH = - 100A IOH = - 6mA VOL LOW Level Output Voltage IOL = 100A IOL = 6mA II IOZ IOFF IDD Input Leakage Current 3- STATE Output Leakage V1 = 0.0V, V1 = 1.8V 0 VO 3.6V VI = VIH or VIL 0 1.8 1.8 1. 8 VDD - 0.2 1. 4 0.2 0. 3 5.0 10 10 20 20 A Conditions VDD M in. 0.7 x VDD 0.2 x VDD V Typ. M ax. Units
Power- OFF Leakage Current 0 (VI,VO) 3.6V Quiescent Supply Current VI = VDD or GND VDD (VI,VO) 3.6V
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PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
AC Electrical Characteristics(1)
TA = -40C to +85C, CL = 30pF, RL = 500 VDD = 3.3V 0.3V VDD = 2.5V 0.2V Symbol tPLH, tPHL tPLH, tPHL tPZH, tPZL tPHZ, tPLZ Parame te rs Prop Delay, DTOQ Prop Delay, LE to Q Output Enable Time Output Disable Time M in. 0 .8 0 .8 0 .8 0 .8 M ax. 3.0 3.0 3.5 3.5 0.5 M in. 1.0 1.0 1.0 1.0 M a x. 3.4 3.9 4. 6 3.8 0.5 VDD = 1.8V M in. 1.5 1.5 1.5 1.5 M a x. 6.0 6.0 7 .0 5.0 0 .5 ns Units
tOSHL, tOSLH Output to Output Skew(2)
Notes: 1. For CL = 50pF add approximatly 300ps to AC maximum specification. 2. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH or LOW (tOSHL) or LOW to HIGH (tOSLH).
AC Setup Requirements
TA = -40C to +85C, CL = 30pF, RL = 500 VDD =3.3V 0.3V Symbol tSU tH tW Parame te rs Setup Time, D to LE Hold Time, D to LE LE Pulse Width, High M in. 1. 5 1.0 1.5 Typ. VDD =2.5V 0.2V M in. 1. 5 1.0 1. 5 Typ. VDD =1.8V M in. 2 .5 1.0 3 .0 ns Typ. Units
Dynamic Switching Characteristics
Symbol VOLP Parame te rs Quiet Output Dynamic Peak VOL Conditions CL = 50pF, VIH = VDD, VIL = 0V VDD 1.8 2.5 3.3 1.8 2.5 3.3 1.8 2.5 3.3 TA = +25C Typical 0.25 0.6 0.8 - 0.25 - 0.6 - 0.8 1.5 1.9 2.2 V Units
VOLP
Quiet Output Dynamic Valley VOL CL = 50pF, VIH = VDD, VIL = 0V
VOLP
Quiet Output Dynamic Valley VOH CL = 50pF, VIH = VDD, VIL = 0V
Capacitance
Symbol CIN COUT C PD Parame te rs Input Capacitance Output Capacitance Power Dissipation Capacitance Conditions VDD = 1.8, 2.5V or 3.3V, VI = 0V or VDD VI = 0V or VDD, VDD = 1.8V, 2.5V or 3.3V VI = 0V or VDD, F = 10 MHz VDD = 1.8V, 2.5V or 3.3V
6
TA = +25C Typical 6 7 20
Units
pF
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PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
Test Circuits and Switching Waveforms
Parameter Measurement Information (VDD = 1.8V - 3.6V)
Switch Position
Te s t tPD
2 x VDD
S1 Open 2 x VDD GND
tPLZ/tPZL
From Output Under Test
R1 500 Open 30pF CL
(See Note A)
tPHZ/tPZH
RL 500
GND
Pulse Width
VDD Low-High-Low Pulse tW VDD VDD/2 0V
Setup, Hold, and Release Timing
Data Input tSU Timing Input tH VDD VDD/2 0V VDD VDD/2 0V
High-Low-High Pulse
VDD/2 0V
Propagaton Delay
VDD VDD/2 Input tPLH tPHL 0V VDD
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. * All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2ns, tF 2ns, measured from 10% to 90%, unless otherwise specified. * The outputs are measured one at a time with one transition per measurement.
Output tPHL Opposite Phase Input Transition tPLH
VDD/2 VOL VDD VDD/2 0V
Enable Disable Timing
VDD Output Control
(Active LOW)
VDD/2 tPZL VDD VDD/2 +0.15V tPZH VDD/2 0V tPHZ -0.15V VOH VOL tPLZ 0V VDD
Output Waveform 1 S1 at 2xVDD
(see Note B)
Output Waveform 2 S1 at GND
(see Note B)
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PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
Packaging Mechanical: 48-pin TSSOP (A)
48
.236 .244
6.0 6.2
1
.488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
.0197 BSC 0.50
.007 .010 0.17 0.27
.002 .006 0.05 0.15
Ordering Information
Ordering Code PI74VCX16373A PI74VCX16373AE Package Code A A Package Type 48-pin TSSOP Pb-free & Green, 48-pin TSSOP
Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free & Green * Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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